Embedded Systems Error Code
Systems & Devices
Embedded Systems

BUSFAULT | Bus fault exception

Industry
Systems & Devices
Canonical
/systems/embedded-systems/error-codes/busfault/
Last Updated
Feb 27, 2026
Summary

The CPU trapped on a bus access error when reading or writing memory or peripherals.

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What This Code Means

Bus faults are raised on many Cortex‑M systems when a memory or peripheral bus access fails. Examples include accessing invalid addresses, misaligned accesses on constrained buses, or peripheral access while a clock is disabled.

Where Users Usually See This Code

  • Fault handler logs
  • During peripheral initialization or I/O operations

Why This Code Appears

  • Invalid pointer to peripheral/memory map
  • Clock/gating configuration makes a peripheral inaccessible
  • Misconfigured DMA or bus timing issues
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What Typically Happens Next

  • Device resets or enters fault handler state

What This Code Is Not

  • It is not a user-facing “app error”
  • It is not a safe basis for electrical repair without documentation

Troubleshooting Checklist

  • Capture fault registers and last accessed address when available
  • Validate memory map addresses and peripheral initialization order
  • Review clock enable and power domain settings

Notes And Edge Cases

Some bus faults are intermittent and may correlate with power instability or EMI in field devices.

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Related Codes

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